【講題】Advanced topics in static timing analysis

【演講時間】9月29日(星期二)下午1點30分  

【演講地點】清華大學校本部第二綜合大樓B側8樓A813室

【摘要】

Timing signoff plays a critical role in VLSI design because it serves as the final, mandatory gatekeeper to ensure a manufactured chip operates correctly at its targeted clock frequency and environmental conditions before sending the layout for expensive fabrication (tape-out). This talk will first review the core fundamentals, industry practice, and methodology in foundry technology modeling for static timing analysis(STA). It will then dive into advanced mathematical models for variation-aware STA. The STA techniques developed over the past 3 decades were aimed at modeling synchronous circuits which often go hand-in-hand with the von Neumann architecture. As the latter is considered highly inefficient for AI workloads, the talk will touch on other more efficient architectural alternatives and discuss their implication on the area of STA.